The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2011
Filed:
Jan. 31, 2006
Hervé Fleury, Caen, FR;
Jean-marc Yannou, Colomby sur Thaon, FR;
Hervé Fleury, Caen, FR;
Jean-Marc Yannou, Colomby sur Thaon, FR;
NXP B.V., Eindhoven, NL;
Abstract
An electronic circuit contains groups of flip-flops (-), coupled to data terminals (-) of the circuit and to a functional circuit (). Each group (-) has a clock input for clocking the flip-flops of the group. Each group (-) can be switched between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit () and/or receive signals from the functional circuit () respectively. A test control circuit () can be switched between a functional mode, a test shift mode and a test normal mode. The test control circuit () is coupled to the groups of flip-flops (-) to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode. A clock multiplexing circuit (-) has inputs coupled to the data terminals (-) and outputs coupled to clock inputs of the groups (-). The test control circuit () is coupled to control the clock multiplexing circuit (-) dependent on the mode assumed by the test control circuit (). The clock multiplexing circuit (-) is arranged to substitute clock signals from respective ones of the data terminals (-) temporarily at the clock inputs of respective ones of the groups (-) in the test normal mode.