The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7898851 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 01, 2011

Filed:

Dec. 19, 2007
Applicants:

Hiroshi Maejima, Milpitas, CA (US);

Makoto Hamada, Mountain View, CA (US);

Inventors:

Hiroshi Maejima, Milpitas, CA (US);

Makoto Hamada, Mountain View, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and a voltage generator. In the memory cell unit, memory cells having a charge accumulation layer and a control gate are connected in series. The word lines are connected to the control gates. The driver circuit selects the word lines. The voltage generator generates a first voltage and a second voltage lower than the first voltage. The first voltage is used by the first driver circuit to transfer a voltage to the unselected word line. The second voltage is used by circuits other than the first driver circuit.


Find Patent Forward Citations

Maejima, Hiroshi. (2011). Semiconductor memory device which includes memory cell having charge accumulation layer and control gate (U.S. Patent No. 7898851). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7898851

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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