High bandwidth phase locked loop (pll) with feedback loop including a frequency divider

Abstract

A phase locked loop (PLL) is provided. In one implementation, the PLL includes a multiphase voltage controlled oscillator (VCO) operable to generate an output signal containing one or more phase signals, a programmable divider operable to divide a frequency of the output signal of the multiphase VCO to produce a divided frequency output signal, and a fractional divider to fractionally divide an input phase signal. The fractional divider can include an integer divider operable to receive the input phase signal and divide the input phase signal in accordance with an integer divisor to produce a divided signal as an input to the multiphase VCO, and a phase interpolator operable to select a phase signal from among the one or more phase signals output by the multiphase VCO, to produce an interpolated output signal having a desired frequency resolution.