The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2011

Filed:

Sep. 17, 2010
Applicants:

Terence Neil Thomas, Ottawa, CA;

Stephen J. Davis, Nepean, CA;

Inventors:

Terence Neil Thomas, Ottawa, CA;

Stephen J. Davis, Nepean, CA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatus provide a delayed clock signal to a plurality of serially connected processing elements, such as a bidirectional pipeline processor. The processing elements include forward and reverse processing paths and forward and reverse processing time intervals along the respective paths. The forward and reverse processing time intervals begin when a block of data, such as encryption data, is gated into an individual processing element for processing and terminate when the processed block of data is gated into a subsequent adjacent processing element along the respective forward or reverse processing path. A clock signal distribution circuit provides a clock signal to the plurality of processing elements such that the clock signal arrives at successive processing elements along the clock signal distribution circuit with an increasing amount of delay so that one of the forward or reverse processing time intervals is greater than the other.


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