The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2011

Filed:

Jun. 06, 2008
Applicant:

Chun-wen Yeh, Jhubei, TW;

Inventor:

Chun-Wen Yeh, Jhubei, TW;

Assignee:

MSTAR Semiconductor, Inc., Hsinchu Hsien, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A protection circuit for an NMOS device is provided. The protection circuit includes a cascoding NMOS transistor and an adjusting circuit. The cascoding NMOS transistor is cascoded between the NMOS device and an external voltage source. The adjusting circuit is coupled to the external voltage source, a gate of the cascoding NMOS transistor, and an internal voltage source. The adjusting circuit adjusts the voltage at the gate of the cascoding NMOS transistor according to the voltages of the external voltage source and the internal voltage source so as to protect the NMOS device from a voltage stress caused by the external voltage source.


Find Patent Forward Citations

Yeh, Chun-Wen. (2011). Circuit for protecting nmos device from voltage stress (U.S. Patent No. 7894171). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7894171

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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