The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2011
Filed:
May. 09, 2008
Laura S. Chadwick, Essex Junction, VT (US);
James A. Culp, Downingtown, PA (US);
David J. Hathaway, Underhill, VT (US);
Anthony D. Polson, Jericho, VT (US);
Laura S. Chadwick, Essex Junction, VT (US);
James A. Culp, Downingtown, PA (US);
David J. Hathaway, Underhill, VT (US);
Anthony D. Polson, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.