Balanced and bi-directional bit line paths for memory arrays with programmable memory cells

Abstract

Disclosed is a design structure of an improved large scale memory system and, more particularly, an improved memory system that incorporates an array of memory cells that are subjected to minimal location dependent power variations and that, optionally, allows for bi-directional random access of millions of bits. Specifically, the system architecture provides a consistent amount of bit line resistance in the write and read paths to each memory cell in the array, independent of position, in order to minimize variations in power delivery to the cells and, thereby, allow for optimal cell distributions. The system architecture further allows current to pass in either direction through the cells in order to minimize element electro-migration and, thereby, extend memory cell life.