The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7890728 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 15, 2011

Filed:

Jan. 05, 2005
Applicants:

Takayuki Matsui, Chiba, JP;

Toshimasa Ike, Chiba, JP;

Masahiro Noguchi, Chiba, JP;

Fukuzo Watanabe, Tokyo, JP;

Inventors:

Takayuki Matsui, Chiba, JP;

Toshimasa Ike, Chiba, JP;

Masahiro Noguchi, Chiba, JP;

Fukuzo Watanabe, Tokyo, JP;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory interface device has a write detection section that detects the write of a predetermined unit amount of data by a memory write unit into a memory. A signal generation section generates a signal to notify the memory write unit that readout of data from the memory by a memory readout unit has been completed. A data storage amount measurement device measures an amount of data stored in the memory during the memory write procedures. A memory readout control section generates an interrupt signal with respect to the memory readout unit when the stored data amount in the memory reaches a predetermined readout start storage amount. A timer counts a period in which writing of the predetermined unit amount of the data into the memory by the memory write unit is discontinued and outputs a timeout signal to the memory readout control section when a value of the period count reaches a predetermined timer period. The memory readout control section generates the interrupt signal with respect to the memory readout unit even when the memory readout control section receives the timeout signal output from the timer.


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