Clock and data recovery circuit and communications apparatus including the clock and data recovery circuit

Abstract

A clock and data recovery circuit that includes a unit to output N-phase clocks each of which has a phase shifted from the others by a time Tobtained by dividing a clock period Pby N, a unit to obtain sampling data serially transferred every time T, a unit to convert the sampling data into first N-bit parallel data every period P, a unit to convert the first N-bit parallel data into second N-bit parallel data indicating a change point in the sampling data, and a unit to use the second N-bit parallel data as input of phase information and output third N-bit parallel data indicating substantially a center position of the change point. N is an integer greater than 2 and data of the first N-bit parallel data at a position equal to the position indicated by the third N-bit parallel data is determined to be recovered data.