The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2011

Filed:

Dec. 03, 2008
Applicants:

Sang-sic Yoon, Gyeonggi-do, KR;

Kyung-hoon Kim, Gyeonggi-do, KR;

Inventors:

Sang-Sic Yoon, Gyeonggi-do, KR;

Kyung-Hoon Kim, Gyeonggi-do, KR;

Assignee:

Hynix Semiconductor Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A circuit which can reduce time taken by a clock alignment training operation in a semiconductor memory device is provided. The semiconductor memory device, which includes: a clock inputting unit configured to receive a system clock and a data clock; a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock, wherein the clock dividing unit determines a phase of the data division clock in response to an inversion division control signal; a phase dividing unit configured to generate a plurality of multiple phase data division clocks having respective predetermined phase differences in response to the data division clock; a data serializing unit configured to serialize predetermined parallel pattern data in correspondence with the multiple phase data division clocks; and a signal transmitting unit configured to transmit an output signal of the data serializing unit to the outside.


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