The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7888952 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 15, 2011

Filed:

Nov. 17, 2008
Applicant:

Reiner Franke, Velbert, DE;

Inventor:

Reiner Franke, Velbert, DE;

Assignee:

Atmel Automotive GmbH, Duisburg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A circuit arrangement is provided for balancing a resistance circuit, which has a field-effect transistor as a controllable resistor and a control circuit, by which the field-effect transistor can be controlled with a gate-source voltage so that there is a resistance between a drain electrode and a source electrode of the field-effect transistor in a predefinable ratio to a reference resistor. In a balancing operation mode, a reference current can be set by the drain-source path of the field-effect transistor and by the reference resistor, which depends on a differential voltage between a voltage drop, caused by the reference current at the reference resistor and a voltage drop, caused by the reference current, at the drain-source path of the field-effect transistor.


Find Patent Forward Citations

Franke, Reiner. (2011). Circuit arrangement for balancing a resistance circuit (U.S. Patent No. 7888952). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7888952

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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