The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2011

Filed:

May. 18, 2009
Applicants:

Woon-yong Park, Suwon, KR;

Bum-ki Baek, Suwon, KR;

Inventors:

Woon-Yong Park, Suwon, KR;

Bum-Ki Baek, Suwon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A thin film transistor (TFT) array panel that includes a substrate, a gate wire including a gate pad, a gate insulating layer pattern, a semiconductor layer pattern, an ohmic contact layer pattern, a data wire including a data pad and a drain electrode, and a passivation layer pattern is presented. The passivation layer pattern is formed on the data wire and has contact holes exposing the gate pad, the data pad, and the drain electrode. The passivation layer pattern also has a planar shape that is similar that of the semiconductor layer pattern due to simultaneous etching except for the portions adjoining the drain electrode and the data pad, having a width greater than that of the data wire, and covering a boundary line of the data wire. A pixel electrode is electrically connected to the exposed portion of the drain electrode and contacts the gate insulating layer pattern.


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