The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2011
Filed:
Oct. 20, 2005
Thai Cheng Chua, Cupertino, CA (US);
Cory Czarnik, Saratoga, CA (US);
Christopher Sean Olsen, Fremont, CA (US);
Khaled Z. Ahmed, Anaheim, CA (US);
Philip Allan Kraus, San Jose, CA (US);
Thai Cheng Chua, Cupertino, CA (US);
Cory Czarnik, Saratoga, CA (US);
Christopher Sean Olsen, Fremont, CA (US);
Khaled Z. Ahmed, Anaheim, CA (US);
Philip Allan Kraus, San Jose, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, oxidizing the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. Optionally, the gate dielectric layer may be nitridized prior to oxidizing the gate dielectric layer. In one embodiment, at least portions of the method are performed using processing reactors arranged on a cluster tool.