The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2011
Filed:
Sep. 14, 2009
Applicants:
Firas N. Abughazaleh, Austin, TX (US);
Brian T. Brunn, Austin, TX (US);
Inventors:
Firas N. Abughazaleh, Austin, TX (US);
Brian T. Brunn, Austin, TX (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method and apparatus for reducing parasitic capacitance. A P-well blocked layer is formed directly beneath a parasitic device. The P-well blocked layer significantly increases the resistance underneath the parasitic device. The resistance of the P-well blocked layer, in effect, partially disconnects the parasitic device from the ground terminal to minimize the effective capacitive impedance that is added to the total termination impedance.