The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7886259 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 08, 2011

Filed:

Feb. 12, 2004
Applicants:

Josep Rius Vazquez, Barcelona, ES;

Jose DE Jesus Pineda DE Gyvez, Eindhoven, NL;

Inventors:

Josep Rius Vazquez, Barcelona, ES;

Jose De Jesus Pineda De Gyvez, Eindhoven, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a method and circuit arrangement for determining power supply noise of a power distribution network. The power supply noise is determined by measuring the propagation delay of a delay circuit powered by the power distribution network, wherein the result of the measuring step is used as an indicator of the power supply noise. Thereby, a real-time power supply noise monitoring can be carried out at any point of a power distribution network of an observed circuitry.


Find Patent Forward Citations

Rius Vazquez, Josep. (2011). Method and circuit arrangement for determining power supply noise (U.S. Patent No. 7886259). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7886259

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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