The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7885806 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 08, 2011

Filed:

Mar. 31, 2003
Applicant:

Hiroshi Nakashima, Toyohashi, JP;

Inventor:

Hiroshi Nakashima, Toyohashi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is provided a simulation method of instruction scheduling comprising detecting a loop from an instruction sequence to be simulated, registering an instruction scheduling target instruction sequence in a loop detection state, comparing a current scheduling target instruction sequence with the registered scheduling target instruction sequence for each loop cycle, and skipping, when the current scheduling target instruction sequence matches the registered scheduling target instruction sequence, scheduling of that scheduling target instruction sequence, and newly registering, when the two instruction sequences do not match, the current scheduling target instruction sequence and executing scheduling.


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Nakashima, Hiroshi. (2011). Simulation method and simulation system of instruction scheduling (U.S. Patent No. 7885806). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7885806

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