The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2011
Filed:
May. 10, 2007
Rajiv V. Joshi, Yorktown Heights, NY (US);
Rouwaida N. Kanj, Round Rock, TX (US);
Ying Liu, Austin, TX (US);
Sani R. Nassif, Austin, TX (US);
Jayakumaran Sivagnaname, Austin, TX (US);
Rajiv V. Joshi, Yorktown Heights, NY (US);
Rouwaida N. Kanj, Round Rock, TX (US);
Ying Liu, Austin, TX (US);
Sani R. Nassif, Austin, TX (US);
Jayakumaran Sivagnaname, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.