Low-power, low-area high-speed receiver architecture

Abstract

A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.