The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2011

Filed:

Oct. 06, 2009
Applicants:

Young Seok Choi, Gyeongsangbuk-do, KR;

Yu Ho Jung, Gyeongsangbuk-Do, KR;

Sang Yong Lee, Gyeonggi-Do, KR;

Inventors:

Young Seok Choi, Gyeongsangbuk-do, KR;

Yu Ho Jung, Gyeongsangbuk-Do, KR;

Sang Yong Lee, Gyeonggi-Do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1339 (2006.01);
U.S. Cl.
CPC ...
Abstract

A liquid crystal display device includes first and second substrates facing each other; gate lines and data lines formed on the first substrate such that the gate lines and the data lines intersect each other to define pixel regions; thin film transistors formed at respective intersections of the gate lines and the data lines; a black matrix layer formed on the second substrate such that the black matrix layer corresponds to a region other than the pixel regions; color filter layers extending in an extension direction of the data lines in respective pixel regions; a liquid crystal layer interposed between the first and second substrates; first column spacers formed on one of the first and second substrates such that each first column spacer corresponds to an associated one of the gate lines or to a channel region of an associated one of the thin film transistors to maintain a cell gap between the first and second substrate; and spacer patterns formed on one of the first and second substrates such that each spacer pattern corresponds to at least one of an associated one of the gate lines and an associated one of the data lines, thereby forming a first gap between the spacer pattern and the other substrate facing the spacer pattern, and reducing an amount of liquid crystals filled between the first and second substrates.


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