The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2011

Filed:

Feb. 21, 2010
Applicants:

Luqiong Wu, San Jose, CA (US);

Linda Chu, San Jose, CA (US);

Toan D. DO, San Jose, CA (US);

Jack Chui, Fremont, CA (US);

Praveen Krishnanunni, Santa Clara, CA (US);

Inventors:

Luqiong Wu, San Jose, CA (US);

Linda Chu, San Jose, CA (US);

Toan D. Do, San Jose, CA (US);

Jack Chui, Fremont, CA (US);

Praveen Krishnanunni, Santa Clara, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/094 (2006.01);
U.S. Cl.
CPC ...
Abstract

A level shifter circuit includes first and second transistors that receive a first input signal at control inputs. A level shifted output signal is generated by the first and the second transistors. Third and fourth transistors receive a second input signal at control inputs. The first input signal is an inverse of the second input signal. A first multiplexer circuit is configurable to couple a control input of a fifth transistor to the first and the second transistors. A second multiplexer circuit is configurable to couple a control input of a sixth transistor to the third and the fourth transistors.


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