The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2011

Filed:

Feb. 14, 2007
Applicants:

Jeffrey B. Barton, Goleta, CA (US);

Diane M. Salazar, Santa Barbara, CA (US);

Joseph H. Durham, Santa Barbara, CA (US);

Inventors:

Jeffrey B. Barton, Goleta, CA (US);

Diane M. Salazar, Santa Barbara, CA (US);

Joseph H. Durham, Santa Barbara, CA (US);

Assignee:

Flir Systems, Inc., Wilsonville, OR (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Systems and methods are disclosed for forming interconnects between semiconductor devices in accordance with one or more embodiments of the present invention. For example, a method of forming interconnects between semiconductor devices includes depositing a plurality of first contacts on a plurality of corresponding first pads of a first semiconductor device; forming a plurality of plated contacts on a plurality of corresponding second pads of a second semiconductor device; aligning the plurality of first contacts with the plurality of plated contacts; and joining the plurality of first contacts to the plurality of plated contacts to form the interconnects between the first semiconductor device and the second semiconductor device.


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