The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2011
Filed:
Aug. 05, 2008
Atsushi Hachisuka, Tokyo, JP;
Atsushi Amo, Tokyo, JP;
Tatsuo Kasaoka, Tokyo, JP;
Shunji Kubo, Tokyo, JP;
Atsushi Hachisuka, Tokyo, JP;
Atsushi Amo, Tokyo, JP;
Tatsuo Kasaoka, Tokyo, JP;
Shunji Kubo, Tokyo, JP;
Renesas Electronics Corporation, Kawasaki-shi, JP;
Abstract
A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (), an insulating layer () on the semiconductor substrate (), a plurality of contact plugs () in the insulating layer (), and an insulating layer () where capacitors (), a plurality of contact plugs (), barrier metal layers () and copper interconnections () are formed. Source/drain regions () in the upper surface of the semiconductor substrate () are electrically connected to the copper interconnections (). One of adjacent source/drain regions () in the upper surface of the semiconductor substrate () is electrically connected to the copper interconnection (), while the other is electrically connected to the capacitor ().