The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2011
Filed:
Jun. 06, 2008
Kunihiko Iwamoto, Kyoto, JP;
Arito Ogawa, Toyama, JP;
Yuuichi Kamimuta, Yokohama, JP;
Rohm Co., Ltd., Kyoto-fu, JP;
Hitachi Kokusai Electric Inc., Tokyo, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
CMISFETs having a symmetrical flat band voltage, the same gate electrode material, and a high permittivity dielectric layer is provided for a semiconductor device including n-MISFETs and p-MISFETs, and a fabrication method thereof, the n-MISFETs including: a first metal oxide layer, placed on the 1st gate insulating film, having a composition ratio shown with M1M2O (where M1=Y, La, Ce, Pr, Nd, Sm, Gd, Th, Dy, Ho, Er, Tm, Yb or Lu, M2=Hf, Zr or Ta, and x/(x+y)>0.12); a second metal oxide layer; and a second metal oxide layer, the p-MISFETs including: a second gate insulating filmplaced on the surface of the semiconductor substrate; a third metal oxide layer, placed on the 2nd gate insulating film, having a composition ratio shown with M3zM4wO (M3=Al, M4=Hf, Zr or Ta, and z/(z+w)>0.14); a fourth metal oxide layer; and a second conductive layerplaced on the fourth metal oxide layer