The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2011

Filed:

Mar. 28, 2007
Applicants:

William P. Mulligan, San Jose, CA (US);

Michael J. Cudzinovic, Sunnyvale, CA (US);

Thomas Pass, San Jose, CA (US);

David Smith, San Jose, CA (US);

Neil Kaminar, Boulder Creek, CA (US);

Keith Mcintosh, Newport Beach, AU;

Richard M. Swanson, Los Altos, CA (US);

Inventors:

William P. Mulligan, San Jose, CA (US);

Michael J. Cudzinovic, Sunnyvale, CA (US);

Thomas Pass, San Jose, CA (US);

David Smith, San Jose, CA (US);

Neil Kaminar, Boulder Creek, CA (US);

Keith McIntosh, Newport Beach, AU;

Richard M. Swanson, Los Altos, CA (US);

Assignee:

SunPower Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A solar cell that is readily manufactured using processing techniques which are less expensive than microelectronic circuit processing. In preferred embodiments, printing techniques are utilized in selectively forming masks for use in etching of silicon oxide and diffusing dopants and in forming metal contacts to diffused regions. In a preferred embodiment, p-doped regions and n-doped regions are alternately formed in a surface of the wafer through use of masking and etching techniques. Metal contacts are made to the p-regions and n-regions by first forming a seed layer stack that comprises a first layer such as aluminum that contacts silicon and functions as an infrared reflector, second layer such titanium tungsten that acts as diffusion barrier, and a third layer functions as a plating base. A thick conductive layer such as copper is then plated over the seed layer, and the seed layer between plated lines is removed. A front surface of the wafer is preferably textured by etching or mechanical abrasion with an IR reflection layer provided over the textured surface. A field layer can be provided in the textured surface with the combined effect being a very low surface recombination velocity.


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