Testing phase error of multiple on-die clocks

Abstract

The phase relationship between two clock signals in an integrated circuit (IC) is determined by transforming each of the clock signals into a data word, where bit transitions in the data word represent signal transitions in the clock signal, and comparing the two data words. For example, in an IC having a de-serializer as part of its input/output logic, the clocks are sequentially multiplexed into the de-serializer, which transforms the clocks into parallel-format data words. The resulting words corresponding to the first and second clock signals can then be compared to determine clock signal transition differences and thus the phase relationship between the corresponding clocks signals.