Test pattern evaluation method and test pattern evaluation device

Abstract

Provided are an evaluation method and device of a test pattern which enable an appropriate evaluation in a reliability test with a simulation time reduced and high accuracy. It is assumed that each possible internal state of a cell determined at least by a logic value or a voltage value of an input terminal is a cell state, and each possible state of a transistor determined by a voltage between terminals of the transistor is a transistor state. The method comprises steps of: verifying operation of a semiconductor integrated circuit at a gate level or higher; acquiring an appearance cell state continuously appearing for a predetermined time or more in the operation verification; acquiring an appearance transistor state using the corresponding appearance cell state in the operation verification for each transistor; and calculating a test activity ratio of the transistor using the corresponding appearance transistor state for each transistor.