The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2011

Filed:

Mar. 30, 2009
Applicants:

Takeo Kageyama, Tokyo, JP;

Keishi Takaki, Tokyo, JP;

Naoki Tsukiji, Tokyo, JP;

Norihiro Iwai, Tokyo, JP;

Hitoshzi Shimizu, Tokyo, JP;

Yasumasa Kawakita, Tokyo, JP;

Suguru Imai, Tokyo, JP;

Inventors:

Takeo Kageyama, Tokyo, JP;

Keishi Takaki, Tokyo, JP;

Naoki Tsukiji, Tokyo, JP;

Norihiro Iwai, Tokyo, JP;

Hitoshzi Shimizu, Tokyo, JP;

Yasumasa Kawakita, Tokyo, JP;

Suguru Imai, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01S 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a surface emitting laser element array of low cost and high reliability. The surface emitting laser element array has a substrate having a semiconductor of a first conduction type; and a plurality of surface emitting laser elements each having, above the substrate, an active layer sandwiched between a first conduction type semiconductor layer area and a second conduction type semiconductor layer area and disposed between a upper reflective mirror and a lower reflective mirror, the surface emitting laser elements being separated from each other by an electric separation structure formed having such a depth as to reach the substrate. The first conduction type semiconductor layer area is arranged between the substrate and the active layer. The surface emitting laser element array further has a current blocking layer arranged between the substrate and the first conduction type semiconductor layer area; and two electrodes connected to the first conduction type semiconductor layer area and the second conduction type semiconductor layer area, respectively, and arranged on a side of the current blocking layer opposite to the substrate.


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