The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 01, 2011
Filed:
Jul. 07, 2008
Jason Yuxin LI, Jamestown, NC (US);
Walter A. Wohlmuth, Greensboro, NC (US);
Swaminathan Muthukrishnan, Greensboro, NC (US);
Christian Rye Iversen, Vestbjerg, DK;
Nathaniel Peachey, Oak Ridge, NC (US);
Jason Yuxin Li, Jamestown, NC (US);
Walter A. Wohlmuth, Greensboro, NC (US);
Swaminathan Muthukrishnan, Greensboro, NC (US);
Christian Rye Iversen, Vestbjerg, DK;
Nathaniel Peachey, Oak Ridge, NC (US);
RF Micro Devices, Inc., Greensboro, NC (US);
Abstract
The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance and a drain-to-gate resistance of the FET element and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element, a resistive element, a source-coupled level shifting diode, and a reverse protection diode. Therefore, the ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.