The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2011

Filed:

Oct. 25, 2006
Applicants:

Hirofumi Iwanaga, Kumamoto, JP;

Shigeaki Noumi, Kumamoto, JP;

Hitoshi Morishita, Kumamoto, JP;

Hiroshi Ueda, Kumamoto, JP;

Inventors:

Hirofumi Iwanaga, Kumamoto, JP;

Shigeaki Noumi, Kumamoto, JP;

Hitoshi Morishita, Kumamoto, JP;

Hiroshi Ueda, Kumamoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1345 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a display device which has a narrow screen border, and excellent display equality. The display device according to the present invention comprises a display panel comprising a glass substrate and a source driver IC which is provided along the edge of the glass substrate. The FPC is connected between the source driver ICs. At the substrate end side of the source driver IC, a bump for GND, a bump for analog power supply, a bump for digital power supply, a bump for reference voltage at the positive polarity side, and a bump for reference voltage at the negative polarity side are formed sequentially from the outer side along the flow of current. These bumps for input and the FPC are connected with the lines for input on the glass substrate. The logic signal lines and are formed along the short side of the source driver IC and along the long side at the display area side.


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