The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 01, 2011
Filed:
Nov. 16, 2005
Hirohito Watanabe, Tokyo, JP;
Motofumi Saitou, Tokyo, JP;
Hiroshi Sunamura, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A diffusion layer () is formed in the surface region of a semiconductor substrate (). A control gate electrode () is formed on the substrate. An interlayer dielectric film () covers the entire surface of the substrate. A drain leader line () made of a semiconductor such as n-type polysilicon is led from the drain region, and a source leader line () is led from the source region through the interlayer dielectric film. The drain leader line is surrounded by an annular floating gate (). In erase, for example, the control gate is set to a ground potential, and a positive voltage is applied to the drain leader line to remove electrons in the floating gate to the drain leader line. In write, positive voltages are applied to the control gate electrode and drain leader line to generate CHE and inject hot electrons into the floating gate. This allows to thin the gate insulating film of a flash memory, increase the degree of integration of a nonvolatile memory, and lower the driving voltage.