The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2011

Filed:

Apr. 27, 2007
Applicants:

Tetsuya Hayashi, Yokosuka, JP;

Masakatsu Hoshi, Yokohama, JP;

Yoshio Shimoida, Yokosuka, JP;

Hideaki Tanaka, Yokohama, JP;

Shigeharu Yamagami, Yokohama, JP;

Inventors:

Tetsuya Hayashi, Yokosuka, JP;

Masakatsu Hoshi, Yokohama, JP;

Yoshio Shimoida, Yokosuka, JP;

Hideaki Tanaka, Yokohama, JP;

Shigeharu Yamagami, Yokohama, JP;

Assignee:

Nissan Motor Co., Ltd., Yokohama-shi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device is provided with: a semiconductor substrate of a predetermined electroconduction type; a hetero semiconductor region contacted with a first main surface of the semiconductor substrate and comprising a semiconductor material having a bandgap different from that of the semiconductor substrate; a gate electrode formed through a gate insulator layer at a position adjacent to a junction region between the hetero semiconductor region and the semiconductor substrate; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor substrate; wherein the hetero semiconductor region includes a contact portion contacted with the source electrode, at least a partial region of the contact portion is of the same electroconduction type as the electroconduction type of the semiconductor substrate, and the partial region has an impurity concentration higher than an impurity concentration of at least that partial region of a gate-electrode facing portion in the hetero semiconductor region which is positioned to face toward the gate electrode through the gate insulator layer.


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