The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 01, 2011
Filed:
Mar. 03, 2008
Lawrence D. Radosevich, Muskego, WI (US);
Steven C. Kaishian, Milwaukee, WI (US);
Daniel G. Kannenberg, Waukesha, WI (US);
Timothy A. Roebke, Milwaukee, WI (US);
Andreas A. Meyer, Richmond Heights, OH (US);
Dennis L. Kehl, Benton Harbor, MI (US);
Lee A. Gettelfinger, Brown Deer, WI (US);
Lawrence D. Radosevich, Muskego, WI (US);
Steven C. Kaishian, Milwaukee, WI (US);
Daniel G. Kannenberg, Waukesha, WI (US);
Timothy A. Roebke, Milwaukee, WI (US);
Andreas A. Meyer, Richmond Heights, OH (US);
Dennis L. Kehl, Benton Harbor, MI (US);
Lee A. Gettelfinger, Brown Deer, WI (US);
Rockwell Automation Technologies, Inc., Mayfield Heights, OH (US);
Abstract
A bus system is disclosed for use with switching devices, such as power electronic devices. The system includes generally parallel bus elements that define electrical reference planes, such as for a dc bus. The bus elements are separated from one another by insulative layers, with additional insulative layers being available for separating the system from other circuit components. Portions of the bus elements are extended or exposed to permit connection to the circuit elements, including packaged switching circuits and energy storage or filtering circuits. The bus system may be conformed to a variety of geometric configurations, and substantially reduces parasitic inductance and total loop inductance in the resulting circuitry.