The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2011
Filed:
Dec. 10, 2007
Lei He, Pasadena, CA (US);
Lei He, Pasadena, CA (US);
The Regents of the University of California, Oakland, CA (US);
Abstract
Integrated circuit apparatus and methods are described for inserting multi-Vbuffers within an interconnection tree during routing toward minimization of power under a delay constraint. Insertion of level converters is not necessary within the routing trees of the interconnect tree despite the insertion of the multi-Vbuffers. Techniques are described for controlling the dramatic complexity increment due to simultaneous delay and power consideration and increased buffer choices. Overhead reduction techniques are taught including: sampling based techniques, prediction based pruning techniques (PSP) and (PMP), and escape grid reduction, each of which are directed to multi-Vbuffer insertion. The resultant integrated circuits are routed with substantial power reductions over conventional routing.