The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2011

Filed:

Feb. 27, 2008
Applicants:

Theodoros E. Anemikos, Milton, VT (US);

Jeanne P. Spence Bickford, Essex Junction, VT (US);

Laura S. Chadwick, Essex Junction, VT (US);

Susan K. Lichtensteiger, Essex Junction, VT (US);

Anthony D. Polson, Jericho, VT (US);

Inventors:

Theodoros E. Anemikos, Milton, VT (US);

Jeanne P. Spence Bickford, Essex Junction, VT (US);

Laura S. Chadwick, Essex Junction, VT (US);

Susan K. Lichtensteiger, Essex Junction, VT (US);

Anthony D. Polson, Jericho, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.


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