The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2011

Filed:

Dec. 02, 2003
Applicants:

Shridhar Mukund, San Jose, CA (US);

Mahesh Gopalan, San Jose, CA (US);

Neeraj Kashalkar, Irvine, CA (US);

Inventors:

Shridhar Mukund, San Jose, CA (US);

Mahesh Gopalan, San Jose, CA (US);

Neeraj Kashalkar, Irvine, CA (US);

Assignee:

PMC-Sierra US, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); G06F 9/00 (2006.01); G06F 9/44 (2006.01); G06F 15/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A networking application processor is provided. The processor includes an input socket configured to receive data packets. The processor includes a memory for holding instructions and circuitry configured to access data structures associated with the processing stages. The circuitry configured to access data structures enables a single cycle access to an operand from a memory location. An arithmetic logic unit (ALU) is provided. Circuitry for aligning operands to be processed by the ALU is included. The circuitry for aligning the operands causes the operand to be aligned by a lowest significant bit, wherein the circuitry for aligning the operand supplies an extension to the operand to allow the ALU to process different size operands.


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