The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2011
Filed:
Mar. 24, 2008
David Q. Chow, San Jose, CA (US);
I-kang Yu, Palo Alto, CA (US);
Siew Sin Hiew, San Jose, CA (US);
Abraham Chih-kang MA, Fremont, CA (US);
Ming-shiang Shen, Taipei Hsien, TW;
David Q. Chow, San Jose, CA (US);
I-Kang Yu, Palo Alto, CA (US);
Siew Sin Hiew, San Jose, CA (US);
Abraham Chih-Kang Ma, Fremont, CA (US);
Ming-Shiang Shen, Taipei Hsien, TW;
Super Talent Electronics, Inc., San Jose, CA (US);
Abstract
High integration of a non-volatile memory device (NVMD) is disclosed. According to one aspect of the present invention, a non-volatile memory device comprises an intelligent non-volatile memory (NVM) controller and an intelligent non-volatile memory module. The NVM controller includes a central processing unit (CPU) configured to handle data transfer operations to the NVM module to ensure source synchronous interface, interleaved data operations and block abstracted addressing. The intelligent NVM module includes an interface logic, a block address manager and at least one non-volatile memory array. The interface logic is configured to handle physical block management. The block address manager is configured to ensure a physical address is converted to a transformed address that is accessible to the CPU of the intelligent NVM controller. The transformed address may be an address in blocks, pages, sectors or bytes either logically or physically.