The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2011

Filed:

Aug. 05, 2009
Applicants:

Juun Horie, Tokyo, JP;

Takeshi Yamamoto, Yokohama, JP;

Manami Haraguchi, Yokohama, JP;

Kenta Kubo, Kamakura, JP;

Tomoaki Miyazawa, Tokyo, JP;

Hirokazu Usami, Kawasaki, JP;

Inventors:

Juun Horie, Tokyo, JP;

Takeshi Yamamoto, Yokohama, JP;

Manami Haraguchi, Yokohama, JP;

Kenta Kubo, Kamakura, JP;

Tomoaki Miyazawa, Tokyo, JP;

Hirokazu Usami, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G03G 15/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

An image forming apparatus includes a developer carrying member to which a developing bias is applied. A frequency f of a developing bias waveform, a developing area Swhich is a time-integrated value of a difference between a voltage value of the developing bias and a solid electrostatic image potential VL in a developing period of the developing bias, a collecting area Swhich is a time-integrated value of a difference between the voltage value of the developing bias and VL in a collecting period of the developing bias, and a developing contrast value Vcon are used for defining a range of a value of the developing bias frequency f, a range of a value of a voltage change rate α at VL during transition of the developing bias voltage value from a developing-side voltage to a collecting-side voltage, and a range of a value represented by the formula:{(S1−1.28×S2)×f/Vcon}×exp(−2.0×10×f/Hz).


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