The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2011
Filed:
Feb. 11, 2010
Sang-gab Kim, Seoul, KR;
Min-seok OH, Yongin-si, KR;
Hong-kee Chin, Suwon-si, KR;
Jeong-min Park, Seoul, KR;
Shi-yul Kim, Yongin-si, KR;
Hee-hwan Choe, Incheon-si, KR;
Sang-Gab Kim, Seoul, KR;
Min-Seok Oh, Yongin-si, KR;
Hong-Kee Chin, Suwon-si, KR;
Jeong-Min Park, Seoul, KR;
Shi-Yul Kim, Yongin-si, KR;
Hee-Hwan Choe, Incheon-si, KR;
Abstract
A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and a drain electrode apart form the source electrode on the ohmic contact, a passivation layer having a contact hole to expose the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole. The drain electrode and the source electrode are formed by a photolithography using a negative photoresist pattern. The negative photoresist pattern includes a first portion having a first thickness corresponding to a channel area, a second portion having a second thickness corresponding to a data line area, and a third portion having a third thickness corresponding to another area.