The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2011

Filed:

Jul. 21, 2005
Applicant:

Eiji Nishimori, Kasugai, JP;

Inventor:

Eiji Nishimori, Kasugai, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention presents a control circuit and a control method of DC-DC converter capable of suppressing subharmonic oscillation of coil current even if the on-duty is over 50%. An error amplified signal Vis an output voltage of an error amplifier ERA. An offset voltage unit Veoutputs a lower limit set voltage Vobtained by subtracting offset voltage efrom error amplified signal V. A voltage comparator COMPcompares lower limit set voltage Voutput from offset voltage Ve, and output voltage signal VIL. When the voltage value of output voltage signal VIL is decreased to lower limit set voltage V(region E), the output of voltage comparator COMPchanges from low level to high level. As a result, main transistor FETis set in conductive state. On the other hand, when the voltage value of output voltage signal VIL reaches an error amplified signal V(region E), main transistor FETis set in non-conductive state.


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