Hierarchical analog ic placement subject to symmetry, matching and proximity constraints

Abstract

A placement tool generates an optimal placement for a plurality of device modules within an analog integrated circuit (IC) subject to device matching, symmetry, and proximity constraints by first defining a multiple-level hierarchy of constraint groups, wherein each constraint group consists of elements that are subject to one of the placement constraints. Each element of each constraint group consists of either of one of the device modules or another one of the constraint groups residing at a lower level of the hierarchy. The tool then generates a hierarchical B*-tree representation of a trial placement for the IC including a separate node representing each constraint group of the hierarchy and a separate node for each of device module not included in any of the constraint groups. Each node representing a constraint group defines relative positions within the IC of each the device modules or lower level constraint groups forming the constraint group that are consistent with the placement constraint on the constraint group. The placement tool iteratively perturbs the hierarchical B*-tree to generate a sequence of trial placements for the IC design and then evaluates a cost function for each trial placement to select a best one of the trial placements as the optimal trial placement.