The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2011

Filed:

Mar. 31, 2008
Applicants:

Nathan C. Buck, Underhill, VT (US);

Eric A. Foreman, Fairfax, VT (US);

James C. Gregerson, Hyde Park, NY (US);

Jeffrey G. Hemmett, St. George, VT (US);

Inventors:

Nathan C. Buck, Underhill, VT (US);

Eric A. Foreman, Fairfax, VT (US);

James C. Gregerson, Hyde Park, NY (US);

Jeffrey G. Hemmett, St. George, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods for analyzing timing of an integrated circuit using block-based static statistical timing analysis and for practical worst test definition and debug. The method includes building a timing graph, determining a slack for each of the nodes in the timing graph, and identifying a statistically worst slack for at least one of the nodes. The method further includes replacing this statistically worst slack with a proxy worst slack.


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