The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7873923 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 18, 2011

Filed:

Feb. 28, 2008
Applicants:

Steven E. Charlebois, Jericho, VT (US);

Paul D. Kartschoke, Williston, VT (US);

John J. Reilly, Huntington, VT (US);

Manikandan Viswanath, South Burlington, VT (US);

Inventors:

Steven E. Charlebois, Jericho, VT (US);

Paul D. Kartschoke, Williston, VT (US);

John J. Reilly, Huntington, VT (US);

Manikandan Viswanath, South Burlington, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

Power gating logic cones is described. In one embodiment a method includes synthesizing logic for an integrated circuit (IC) design; identifying low switching nodes within the logic that switch less than a threshold; determining a potential power gating cone (PGC) based on the identified low switching nodes; determining a power gating logic expression for the potential PGC that includes a minimum set of inputs to the potential PGC that are least switching; determining whether energy savings using the power gating logic expression meets a criteria; and accepting the potential PGC in response to meeting the criteria.


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