The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2011
Filed:
Jun. 26, 2007
Masakazu Ishikawa, Hitachi, JP;
Akira Bandou, Hitachi, JP;
Masahiro Shiraishi, Hitachi, JP;
Masamitsu Kobayashi, Hitachi, JP;
Yasuyuki Furuta, Naka, JP;
Akihiro Onozuka, Hitachi, JP;
Shin Kokura, Hitachi, JP;
Eiji Kobayashi, Hitachinaka, JP;
Satoru Funaki, Hitachi, JP;
Takashi Umehara, Hitachi, JP;
Naoya Mashiko, Hitachiota, JP;
Yuusuke Seki, Hitachi, JP;
Tatsuyuki Ootani, Hitachi, JP;
Masakazu Ishikawa, Hitachi, JP;
Akira Bandou, Hitachi, JP;
Masahiro Shiraishi, Hitachi, JP;
Masamitsu Kobayashi, Hitachi, JP;
Yasuyuki Furuta, Naka, JP;
Akihiro Onozuka, Hitachi, JP;
Shin Kokura, Hitachi, JP;
Eiji Kobayashi, Hitachinaka, JP;
Satoru Funaki, Hitachi, JP;
Takashi Umehara, Hitachi, JP;
Naoya Mashiko, Hitachiota, JP;
Yuusuke Seki, Hitachi, JP;
Tatsuyuki Ootani, Hitachi, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi Information & Control Solutions, Ltd., Ibaraki, JP;
Abstract
A programmable electronic controller in which one central arithmetic processing unit and a plurality of input devices and output devices are connected by means of a parallel bus, the controller being basically configured to activate a self-diagnostic function and a diagnostic test of the input devices and the output devices with an instruction from a microprocessor of the central arithmetic processing unit; and to judge the result with the microprocessor of the central arithmetic processing unit, by using the microprocessor installed in the central arithmetic processing unit also as a processor for tests (diagnostic tests) of the self-diagnostic function of the input devices and output devices and conducting tests of the self-diagnostic function of the plurality of input devices and output devices with the central arithmetic processing unit.