The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2011
Filed:
Apr. 02, 2009
Jean-fu Kiang, Taipei, TW;
Shan-yung Yang, Taipei, TW;
Jean-Fu Kiang, Taipei, TW;
Shan-Yung Yang, Taipei, TW;
National Taiwan University, Taipei, TW;
Abstract
Disclosed is a designed and implemented 12-bit 70 Msps pipeline analog-to-digital converter. Two adjacent blocks operate at opposite clock phases to reduce the chip size and power consumption. Since the opposite clock phases are designed to be provided by external devices, the timing between these two clock phases must be accurate. Note that the architecture of pipeline ADC consists of four stages, divided into two groups, wherein two adjacent stages in each group share one 3-bit flash ADC, hence only two 3-bit flash ADCs are required in this scheme. Therefore, there are 6-bit signal produced from each 3-bit flash ADC within one clock phase which consists of two opposite clock phases. And within the same period, the total output of the pipeline analog-to-digital converter would be 12-bit. From the simulation results, when the sampling rate is 70 Msps, this converter consumes 155 mW (TBV) at a ±1.8 V supply.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile