The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2011

Filed:

Jul. 18, 2005
Applicants:

Mihai Adrian Tiberiu Sanduleanu, Eindhoven, NL;

Eduard Stikvoort, Eindhoven, NL;

Inventors:

Mihai Adrian Tiberiu Sanduleanu, Eindhoven, NL;

Eduard Stikvoort, Eindhoven, NL;

Assignee:

ST-Ericsson SA, Geneva, CH;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/20 (2006.01); H03K 19/094 (2006.01);
U.S. Cl.
CPC ...
Abstract

It is disclosed a combinatorial logic circuit comprising a first logic block (B) coupled to a supply terminal (V) via a first resistor means (RI) and via a second resistor means (R) for receiving respective first and second supply currents (). The circuit further comprises a second logic block (B) coupled to the supply terminal (V) via the first resistor means (R) and via the second resistor means (R) for receiving respective third and fourth supply currents (). A first output terminal (Q−) coupled to the first block (B) and to the first resistor means (R). A second output terminal (Q+) coupled to the second logic block (B) and to the second resistor means (R). A first current source (I) coupled to at least one of the first output terminal (Q−) and/or second output terminal (Q+) for providing a first supply current (I) through the first resistor means (R), which is substantially equal to a second supply current (I) through the second resistor means (R).


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