Capacitance cell, semiconductor device, and capacitance cell arranging method

Abstract

A capacitance cellis wired while using adjacent wiring layers Ma and Mb as a pair of electrode layers Tand Torthogonally to opposed lateral end faces out of lateral end faces X, X, Y, and Ythat section the cell in a plane direction. Contact surfaces of electrode surfaces Tand Twith the lateral end faces are second connection terminals Tand T. For longitudinal pathways, first and second via contact layers Vand Vare connected. The first via contact layer Vinterconnects the wiring layers Ma and Mb. The second via contact layer Vis connected to a wiring layer located outside beyond an upper or lower end face Z, Z. The second via contact layer Vis connected to a first connection terminal T, Tlocated on the upper or lower end faces Z, Z. The capacitance cellsare linked via the first and second connection terminals so that a capacitance element having a free shape is formed. A capacitance cell, a semiconductor device, and a capacitance element arranging method that allow to arrange capacitance elements each using wiring layers sandwiching an interlayer insulating film with less of a leak current as electrode layers according to the shapes of unused areas.