The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2011
Filed:
Jul. 05, 2007
Jyh Ming Jong, Fremont, CA (US);
Tomonori Hirai, Fremont, CA (US);
Jyh Ming Jong, Fremont, CA (US);
Tomonori Hirai, Fremont, CA (US);
Mitac International Corp., Taoyuan, TW;
Abstract
A clocking scheme is provided to synchronize system clock across plural independent SMP (Symmetric Multi-Processing) domains of the multi-processor system. Each of the SMP domains is connected with another through an interconnection board and two or more identical connectors. The clocking scheme includes a clock source, a SPLL (Select Phase-Locked Loop) and a clock buffer on each of the SMP domains to provide a dedicated base clock. A self-clock path is used to send the base clock from the clock source to the SPLL on the same SMP domain, and on the other hand one or more base clock is sent through a distribution-clock path to another SPLL. The distribution-clock path and the self-clock path will have equal lengths, making the base clock pass through the two connectors or the same connector twice to achieve the similar electrical characteristics and balance the skew or propagation delay.