The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2011

Filed:

Jun. 29, 2008
Applicants:

Hirak Mitra, Sunnyvale, CA (US);

Raj Kulkarni, Sunnyvale, CA (US);

Richard Wicks, Sunnyvale, CA (US);

Michael Moon, Sunnyvale, CA (US);

Inventors:

Hirak Mitra, Sunnyvale, CA (US);

Raj Kulkarni, Sunnyvale, CA (US);

Richard Wicks, Sunnyvale, CA (US);

Michael Moon, Sunnyvale, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/167 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present disclosure provides an architecture that enables massive parallel processing on an IC while alleviating control congestion, memory access congestion and wiring congestion, together with high flexibility where the processing units are soft-arranged to perform different tasks. In an embodiment, the present architecture includes a functional block with a GO component to start the functional block, and a DONE component to identifying the completion status. The GO and DONE components can be linked together, preferably by a linkage component, to chain the functional blocks. The linkage is preferably soft configurable. In another embodiment, the present architecture includes an integrated circuit comprises a plurality of functional blocks chained together for serial processing, parallel processing, or any combination thereof.


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