The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2011

Filed:

May. 19, 2008
Applicants:

Ji-hoon Bang, Yongin-si, KR;

Kwang-chul Kim, Seoul, KR;

Inventors:

Ji-Hoon Bang, Yongin-si, KR;

Kwang-Chul Kim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/76 (2006.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
Abstract

A reconfigurable processor (RP) structure is provided, and particularly, a multi-mode providing apparatus including an exclusive coarse-grained array unit for each mode and a multi-mode providing method thereof are provided. The multi-mode providing apparatus includes: at least one reconfigurable operation mode execution unit performing a plurality of operations for processing a predetermined operation mode; a common coarse-grained array unit shared temporally by the at least one reconfigurable operation mode execution unit, and performing a main processing operation set to be performed by the common coarse-grained array unit, among the plurality of operations; and a controller determining whether the common coarse-grained array unit is available, and according to the result of the determination controlling the at least one reconfigurable operation mode execution unit so that the common coarse-grained array unit or an exclusive coarse-grained array unit performs the main processing operation, the exclusive coarse-grained array unit included in the at least one reconfigurable operation mode execution unit. Therefore, it is possible to reduce a delay time for data processing while reducing the size of hardware.


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