The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2011
Filed:
May. 12, 2006
John M. Thendean, Berkeley, CA (US);
Jennifer Wong, Fremont, CA (US);
Bernard J. New, Carmel Valley, CA (US);
Alvin Y. Ching, Sunnyvale, CA (US);
James M. Simkins, Park City, UT (US);
Anna Wing Wah Wong, Santa Clara, CA (US);
Vasisht Mantra Vadi, San Jose, CA (US);
John M. Thendean, Berkeley, CA (US);
Jennifer Wong, Fremont, CA (US);
Bernard J. New, Carmel Valley, CA (US);
Alvin Y. Ching, Sunnyvale, CA (US);
James M. Simkins, Park City, UT (US);
Anna Wing Wah Wong, Santa Clara, CA (US);
Vasisht Mantra Vadi, San Jose, CA (US);
Xilinx Inc., San Jose, CA (US);
Abstract
An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.